Hardware IP block for in-chip memory compression offload
This technology describes a hardware memory controller that works closely with an operating system to decide when and how to compress memory used by running programs. Instead of the OS making all compression decisions in software, the controller reads policy instructions written directly into a shared data structure called a control block, allowing hardware to act on compression goals set by the OS. This split responsibility means compression decisions happen faster and with less CPU overhead than pure software approaches. The design supports multiple processes simultaneously, each with its own allocation objectives, giving the system fine-grained control over memory efficiency.
What you could build
A hardware IP block or chiplet feature licensed to SoC designers and memory controller vendors, enabling more efficient memory utilization in servers, edge devices, or high-performance embedded systems. Data center chip designers and hyperscaler custom silicon teams would be the primary buyers.
Who in Virginia should care
Northern Virginia hyperscalers and data center operators, as well as defense contractors building high-density compute systems, would have interest in memory efficiency IP.
Readiness: Concept
Concept — described but not yet demonstrated. Lab validated — supported by experimental results in the patent. Prototype likely — the text describes a built, working embodiment.
Readiness is inferred from the patent text, not from a lab visit.
The record
- Inventors
- Xun Jian, Gagandeep Panwar, Muhammad Laghari, Yuqing Liu
- Filed
- Patent pending — filed September 24, 2025
- Status
- Application
- Publication number
- US20260086934A1
Ready to talk?
Virginia Tech Intellectual Properties handles licensing for this technology.
Prosim summaries are generated from public patent text and are not legal advice.