Multilayer low-parasitics semiconductor power package
This technology describes a compact way to stack and package semiconductor components—such as power transistors or chips—into a single unit using alternating layers of conductive and insulating materials, with openings cut through each layer so the chip remains accessible for wire bonding to multiple electrical connections above it. The layered structure lets engineers connect different terminals of the chip to different conductive layers independently, reducing unwanted electrical interference (parasitic effects) that normally degrades performance. The result is a smaller-footprint package that can handle multiple electrical connections more cleanly than conventional flat packaging approaches.
What you could build
A compact multilayer power semiconductor package suitable for power converters, motor drives, or RF modules; the likely buyers are power electronics manufacturers and chip packaging foundries seeking higher-density, lower-parasitics solutions for industrial or automotive applications.
Who in Virginia should care
Defense electronics primes and power electronics suppliers in Northern Virginia and the broader Hampton Roads corridor would have interest, given the packaging density and parasitics benefits relevant to military-grade and aerospace power modules.
Readiness: Prototype likely
Concept — described but not yet demonstrated. Lab validated — supported by experimental results in the patent. Prototype likely — the text describes a built, working embodiment.
Readiness is inferred from the patent text, not from a lab visit.
The record
- Inventors
- Kaushik Rajashekara, Ruxi Wang, Zheng Chen, Dushan Boroyevich
- Granted
- September 9, 2014
- Status
- Granted patent
- Patent number
- 8829692
Ready to talk?
Virginia Tech Intellectual Properties handles licensing for this technology.
Prosim summaries are generated from public patent text and are not legal advice.