Runtime FPGA reconfiguration without pre-assigned chip regions
This technology enables FPGAs — programmable computer chips used in high-performance and specialized computing — to be reconfigured on the fly from a remote server, without needing to pre-plan exactly where each functional module will sit on the chip. A server receives a request to change what the FPGA is doing, computes the necessary reprogramming instructions using a library of pre-built modules, and sends only the relevant partial update to the chip rather than reprogramming it entirely. The key innovation is that modules can be placed flexibly wherever space exists in the chip's reconfigurable region, rather than being locked to fixed zones — making the system more efficient and adaptive at runtime.
What you could build
A middleware platform or cloud service that manages dynamic FPGA reconfiguration for edge computing, defense signal processing, or data center accelerator cards; buyers would be hardware OEMs, defense contractors, and cloud infrastructure providers deploying FPGA-accelerated workloads.
Who in Virginia should care
Northern Virginia's dense concentration of defense contractors (Leidos, Booz Allen, SAIC) and data center operators using FPGA accelerators would be natural evaluators of this technology.
Readiness: Lab validated
Concept — described but not yet demonstrated. Lab validated — supported by experimental results in the patent. Prototype likely — the text describes a built, working embodiment.
Readiness is inferred from the patent text, not from a lab visit.
The record
- Inventors
- Cameron PATTERSON, Peter Athanas, John K. Bowen, Timothy G. Dunham, Justin D. Rice, Matthew T. Shelburne, Jorge A. Suris, Pletri, Jonathan Graf
- Granted
- March 8, 2011
- Status
- Granted patent
- Patent number
- 7902866
Ready to talk?
Virginia Tech Intellectual Properties handles licensing for this technology.
Prosim summaries are generated from public patent text and are not legal advice.