Complete fault-coverage engine for chip test pattern
This technology is a smarter way to find every possible input combination that can trigger a specific fault or state in a computer chip during testing. It uses a connectivity-aware search strategy to prioritize which parts of the circuit to examine, combined with a learning technique that recognizes when the same situation has been seen before and reuses that knowledge rather than repeating work. The result is a more compact, complete set of test patterns generated faster than brute-force approaches. In practical terms, chip manufacturers use this to verify that their test suites actually catch defects before shipping silicon.
What you could build
A software engine or plugin for EDA (electronic design automation) toolchains that accelerates and completes automatic test pattern generation for chip manufacturers and fabless semiconductor companies; buyers are semiconductor design teams and chip test engineers at companies like Intel, Qualcomm, or TSMC design partners.
Who in Virginia should care
Defense primes and government contractors in the NoVA/DC corridor (e.g., Northrop Grumman, Leidos, Booz Allen) that work on trusted microelectronics and hardware assurance programs would have direct interest.
Readiness: Prototype likely
Concept — described but not yet demonstrated. Lab validated — supported by experimental results in the patent. Prototype likely — the text describes a built, working embodiment.
Readiness is inferred from the patent text, not from a lab visit.
The record
- Inventors
- Michael S. Hsiao, Kameshwar Chandrasekar
- Granted
- April 8, 2008
- Status
- Granted patent
- Patent number
- 7356747
Ready to talk?
Virginia Tech Intellectual Properties handles licensing for this technology.
Prosim summaries are generated from public patent text and are not legal advice.