Edge termination structures for higher-voltage SiC power
This patent describes a manufacturing process for making better edge termination structures on power semiconductors — the zones at the edge of a chip that prevent electrical breakdown. The key innovation is using two stacked photoresist layers with different etch rates alongside a wet etch step to carve a precisely angled (beveled) profile into a dielectric layer, which then acts as a graded mask during ion implantation. This graded implant profile reduces the electric field crowding at device edges that typically causes premature failure in high-voltage devices like MOSFETs, diodes, and IGBTs. The result is a more reliable, higher-voltage-rated power semiconductor device made using process steps compatible with existing fab infrastructure.
What you could build
A process module licensed to power semiconductor fabs or IDMs to improve termination yield and voltage ratings in SiC or Si power devices; target buyers are companies designing discrete power components for EV drivetrains, industrial drives, and power converters.
Who in Virginia should care
Defense primes and government contractors in Northern Virginia requiring high-reliability power electronics, plus semiconductor equipment and materials companies in the broader Mid-Atlantic corridor.
Readiness: Lab validated
Concept — described but not yet demonstrated. Lab validated — supported by experimental results in the patent. Prototype likely — the text describes a built, working embodiment.
Readiness is inferred from the patent text, not from a lab visit.
The record
- Inventors
- Yuhao Zhang, Ming Xiao
- Granted
- April 21, 2026
- Status
- Granted patent
- Patent number
- 12610764
Ready to talk?
Virginia Tech Intellectual Properties handles licensing for this technology.
Prosim summaries are generated from public patent text and are not legal advice.